1. Field of the Invention
The present invention generally relates to the field of field effect transistors (FETs) with fin structure. More particularly, the present invention relates to the structure of a field effect transistor with fin structure and fabricating method thereof.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin structure of the silicon substrate, and accordingly, the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect is therefore reduced. The channel region is also longer under the same gate length, and thus the current between the source and the drain is increased. In addition, threshold voltage of the fin FET can further be controlled by adjusting the work function of the gate.
In a conventional three-dimensional structure of the FET with fin structure, after the formation of a fin structure, an anti-punch ion implantation process is carried out to prevent the occurrence of a punch-through effect between source/drain or in a substrate. In a case that the top surface of the fin structure is covered by a patterned mask layer, however, exposed sidewalls of the fin structure are easily contaminated during the performance of the anti-punch ion implantation process. Because a channel layer is always disposed near the surface of the fin structure, the above mentioned contamination would affect the doping concentration in the channel layer and further increase the variation of carrier mobility in the channel layer.
In order to overcome the above-mentioned drawbacks, there is a need to provide a novel method for fabricating a FET which can avoid the contamination of the channel layer and therefore improve the electrical consistency among each FETs.